View SC68C752BIB48_7970529.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. general description the sc68c752b is a dual universal asynch ronous receiver/transmitter (uart) with 64-byte fifos, automatic hardware/software fl ow control, and data rates up to 5 mbit/s. the sc68c752b offers enhanced features. it has a transmission co ntrol register (tcr) that stores receiver fifo threshold levels to start/stop transmission during hardware and software flow control. with the fifo rdy register, the software gets the status of txrdyn /rxrdyn for all four ports in one access. on-chip status registers provide the user with error indications, operational status, and modem interface control. system interrupts may be tailored to meet user requirements. an internal loopba ck capability allows on-board diagnostics. the uart transmits data, sent to it over th e peripheral 8-bit bus, on the txn signal and receives characters on the rxn signal. charac ters can be programmed to be 5 bits, 6 bits, 7 bits, or 8 bits. the uart has a 64-byte receive fifo and transmit fifo and can be programmed to interrupt at different trigger levels. the uart generates its own desired baud rate based upon a programmable divisor and its input clock. it can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. the receiver can detect break, idle, or framing errors, fifo overflow, and parity errors. the transmitter can detect fifo underflow. the uart also contains a software interface for modem control operations, and has software flow control and hardware flow control capabilities. the sc68c752b is available in lqfp48 and hvqfn32 packages. 2. features ? dual channel with 68 mode (motorola) p interface ? up to 5 mbit/s data rate ? 64-byte transmit fifo ? 64-byte receive fifo with error flags ? programmable and selectable transmit and receive fifo trigger levels for dma and interrupt generation ? software/hardware flow control ? programmable xon/xoff characters ? programmable auto-rts and auto-cts ? optional data flow resume by xon any character ? dma signalling capability for both received and transmitted data ? supports 5 v, 3.3 v and 2.5 v operation sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos and 68 mode p interface rev. 04 ? 20 january 2010 product data sheet
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 2 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos ? 5 v tolerant on input only pins 1 ? software selectable baud rate generator ? prescaler provides additional divide-by-4 function ? industrial temperature range ( ? 40 c to +85 c) ? fast data bus access time ? programmable sleep mode ? programmable serial interface characteristics ? 5-bit, 6-bit, 7-bit, or 8-bit characters ? even, odd, or no parity bit generation and detection ? 1, 1.5, or 2 stop bit generation ? false start bit detection ? complete status reporting capabilit ies in both normal and sleep mode ? line break generation and detection ? internal test and loopback capabilities ? fully prioritized inte rrupt system controls ? modem control functions (cts , rts , dsr , dtr , ri , and cd ) 3. ordering information 1. for data bus pins d7 to d0, see table 25 ? limiting values ? . table 1. ordering information type number package name description version SC68C752BIB48 lqfp48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm sot313-2 sc68c752bibs hvqfn32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 5 0.85 mm sot617-1
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 3 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 4. block diagram fig 1. block diagram of sc68c752b txa, txb rxa, rxb sc68c752b xtal2 xtal1 d0 to d7 r/w reset 002aab017 data b u s and control logic register select logic a0 to a3 cs interrupt control logic irq txrdya, txrdyb rxrdya, rxrdyb clock and baud rate generator interconnect bus lines and control signals modem control logic dtrs, dtrb rtsa, rtsb opa, opb ctsa, ctsb ria, rib cda, cdb dsra, dsrb receive shift register receive fifo register flow control logic flow control logic transmit shift register transmit fifo register
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 4 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 5. pinning information 5.1 pinning fig 2. pin configuration for lqfp48 fig 3. pin configuration for hvqfn32 SC68C752BIB48 d5 reset d6 dtrb d7 dtra rxb rtsa rxa opa txrdyb rxrdya txa irq txb n.c. opb a0 cs a1 a3 a2 n.c. n.c. xtal1 d4 xtal2 d3 r/w d2 cdb d1 gnd d0 rxrdyb txrdya v cc v cc dsrb ria rib cda rtsb dsra ctsb gnd ctsa n.c. 002aab018 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24 002aac01 4 sc68c752bibs transparent top view a2 opb cs a1 txb a0 txa n.c. rxa irq rxb opa d7 rtsa d6 reset a3 xtal1 xtal2 r/w gnd n.c. rtsb ctsb d5 d4 d3 d2 d1 d0 v cc ctsa 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 5 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 5.2 pin description table 2. pin description symbol pin type description lqfp48 hvqfn32 a0 28 19 i address 0 select bit. internal register s address selection. a1 27 18 i address 1 select bit. internal register s address selection. a2 26 17 i address 2 select bit. internal register s address selection. a3 11 9 i address 3. a3 is used to select channel a or channel b. a logic low selects channel a, and a logic high selects channel b. (see ta b l e 3 .) cda 40 - i carrier detect (active low). these inputs are associated with individual uart channel a and channel b. a logic low on these pins indicates that a carrier has been detected by the modem for that c hannel. the state of these inputs is reflected in the modem status register (msr). cdb 16 - i cs 10 8 i chip select (active low). this pin enables data transfers between the user cpu and the sc68c752b for the channel(s) addressed. individual uart sections (a, b) are addressed by a3. see ta b l e 3 . ctsa 38 25 i clear to send (active low). these inputs are associated with individual uart channel a and channel b. a logic 0 (low) on the ctsn pins indicates the modem or data set is ready to accept tr ansmit data from the sc68c752b. status can be tested by reading msr[4]. these pi ns only affect the transmit and receive operations when auto-cts function is enabled via the enhanced feature register efr[7] for hardwar e flow control operation. ctsb 23 15 i d0 44 27 i/o data bus (bidirectional). these pins are the 8-bit, 3-state data bus for transferring information to or from the co ntrolling cpu. d0 is the least significant bit and the first data bit in a transmit or receive serial data stream. d1 45 28 i/o d2 46 29 i/o d3 47 30 i/o d4 48 31 i/o d5 1 32 i/o d6 2 1 i/o d7 3 2 i/o dsra 39 - i data set ready (active low). these inputs are associated with individual uart channel a and channel b. a logic 0 (low) on these pins indicates the modem or data set is powered-on and is ready for data exchange with the uart. the state of these inputs is reflect ed in the modem status register (msr). dsrb 20 - i dtra 34 - o data terminal ready (active low). these outputs are associated with individual uart channel a and channel b. a logic 0 (low) on these pins indicates that the sc68c752b is powered-on and ready. these pins can be controlled via the modem control register. writing a logic 1 to mcr[0] will set the dtrn output pin to logic 0 (low), enabling the modem. the output of these pins will be a logic 1 after writing a logic 0 to mcr[0], or after a reset. dtrb 35 - o gnd 17, 24 13 [1] i signal and power ground. irq 30 21 o interrupt request. interrupts from uart channel a and channel b are wire-ored internally to function as a single irq interrupt. this pin transitions to a logic 0 (if enabled by the interrupt enable register) whenever a uart channel(s) requires service. individual channel interrupt status can be determined by addressing each channel through its associated internal register, using cs and a3. an external pull-up resistor must be connected between this pin and v cc .
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 6 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos r/w 15 12 i a logic low on this pin will transfer the contents of the data bus (d[7:0]) from an external cpu to an internal register that is defined by address bits a[2:0]. a logic high on this pin will load the contents of an internal register defined by address bits a[2:0] on the sc68c752b data bus (d[7:0]) for access by an external cpu. n.c. 12, 25, 29, 37 14, 20 - not connected opa 32 22 o user defined outputs. this function is associated with individual channel a and channel b. the state of these pins is defin ed by the user through the software settings of mcr[3]. opa /opb is a logic 0 when mcr[3] is set to a logic 1. opa /opb is a logic 1 when mcr[3] is set to a logic 0. the output of these two pins is high after reset. opb 97 o reset 36 24 i reset (active low). this pin will reset the internal registers and all the outputs. the uart transmitter output and the receiver input will be disabled during reset time. reset is an active low input. ria 41 - i ring indicator (active low). these inputs are associated with individual uart channel a and channel b. a logic 0 on these pins indicates the modem has received a ringing signal from the tele phone line. a low-to-high transition on these input pins generates a modem stat us interrupt, if enabled. the state of these inputs is reflected in the modem status register (msr). rib 21 - i rtsa 33 23 o request to send (active low). these outputs are associated with individual uart channel a and channel b. a logic 0 on the rtsn pin indicates the transmitter has data ready and waiting to send. writing a logic 1 in the modem control register mcr[1] will set this pin to a logic 0, indicating data is available. after a reset these pins are set to a logic 1. these pins only affect the transmit and receive operations when auto-rts function is enabled via the enhanced feature register (efr[6]) for hardware flow control operation. rtsb 22 16 o rxa 5 4 i receive data input. these inputs are associated with individual serial channel data to the sc68c752b. during the local loopback mode, these rxn input pins are disabled and transmit data is connected to the uart receive input internally. rxb 4 3 i rxrdya 31 - o receive ready (active low). rxrdya or rxrdyb goes low when the trigger level has been reached or the fifo has at least one character. it goes high when the receive fifo is empty. rxrdyb 18 - o txa 7 5 o transmit data a, b. these outputs are associated with individual serial transmit channel data from the sc68c752b. during the local loopback mode, the txn output pin is disabled and transmit data is internally connected to the uart receive input. txb 8 6 o txrdya 43 - o transmit ready (active low). txrdya or txrdyb go low when there are at least a trigger level number of spaces available or when the fifo is empty. it goes high when the fifo is full or not empty. txrdyb 6- o v cc 19, 42 26 i power supply input. xtal1 13 10 i crystal or external clock input. functions as a crystal input or as an external clock input. a crystal can be connected between xtal1 and xtal2 to form an internal oscillator circuit (see figure 13 ). alternatively, an external clock can be connected to this pin to provide custom data rates. xtal2 14 11 o output of the crystal oscillator or buffered clock. (see also xtal1.) xtal2 is used as a crystal oscillator output or a buffered clock output. table 2. pin description ?continued symbol pin type description lqfp48 hvqfn32
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 7 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos [1] hvqfn32 package die supply ground is connec ted to both gnd pin and exposed center p ad. gnd pin must be connected to supply ground for proper device operation. for enhanced thermal, electric al, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the pcb in the thermal pad region. 6. functional description the uart will perform serial-to- parallel conversion on data characters received from peripheral devices or modems, and parallel-to-parallel conversion on data characters transmitted by the processor. the complete status of each channel of the sc68c752b uart can be read at any time during functional operation by the processor. the sc68c752b can be placed in an alternat e mode (fifo mode) relieving the processor of excessive software overhead by bufferin g received/transmitted characters. both the receiver and transmitter fifos can store up to 64 bytes (including three additional bits of error status per byte for the receiver fifo ) and have selectable or programmable trigger levels. primary outputs rxrdyn and txrdyn allow signalling of dma transfers. the sc68c752b has selectable hardware flow control and software flow control. hardware flow control signif icantly reduces software overhead and increases system efficiency by automatically controllin g serial data flow using the rtsn output and ctsn input signals. software flow control autom atically controls data flow by using programmable xon/xoff characters. the uart includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (2 16 ? 1). 6.1 trigger levels the sc68c752b provides independent selectable and programmable trigger levels for both receiver and transmitter dma and interrupt generation. after reset, both transmitter and receiver fifos are disabled and so, in effe ct, the trigger level is the default value of one byte. the selectable trigger levels are available via the fcr. the programmable trigger levels are available via the trigger level register (tlr). 6.2 hardware flow control hardware flow control is comprised of auto-cts and auto-rts . auto-cts and auto-rts can be enabled/disabled independently by programming efr[7:6]. with auto-cts , ctsn must be active before the uart can transmit data. auto-rts only activates the rtsn output when there is enough room in the fifo to receive data and de-activates the rtsn output when the receive fi fo is sufficiently full. the halt and resume trigger levels in th e tcr determine the le vels at which rtsn is activated/deactivated. table 3. channel selection using cs pin cs a3 uart channel 1 - none 0 0 channel a 0 1 channel b
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 8 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos if both auto-cts and auto-rts are enabled, when rtsn is connected to ctsn , data transmission does not occur unless the rece ive fifo has empty space. thus, overrun errors are eliminated during hardware flow control. if not enabled, overrun errors occur if the transmit data rate exceeds the receive fifo servicing latency. 6.2.1 auto-rts auto-rts data flow control originates in the receiver block (see figure 1 ? block diagram of sc68c752b ? on page 3 ). figure 5 shows rtsn functional timing. the receiver fifo trigger levels us ed in auto-rts are stored in the tcr. rtsn is active if the receiver fifo level is below the halt trigger level in tcr[3:0]. when the receiver fifo halt trigger level is reached, rtsn is de-asserted. the sending device (for example, another uart) may send an additional byte after the trigger level is reached (assuming the sending uart has another byte to send) because it may not recognize the de-assertion of rtsn until it has begun sending the additional byte. rtsn is automatically reasse rted once the receiver fifo reaches the resume trigger level progra mmed via tcr[7:4]. this re-assertion allows the sending device to resume transmission. fig 4. auto flow control (auto-rts and auto-cts ) example receive fifo flow control transmit fifo parallel to serial transmit fifo receive fifo uart 1 uart 2 d7 to d0 rxn txn rtsn ctsn txn rxn ctsn rtsn d7 to d0 002aaf090 serial to parallel serial to parallel flow control flow control flow control parallel to serial n = receiver fifo trigger level. the two blocks in dashed lines cover the case w here an additional byte is sent, as described in section 6.2.1 . fig 5. rtsn functional timing start byte n start byte n + 1 start stop stop rxn rtsn r/w n n + 1 12 002aab086
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 9 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6.2.2 auto-cts the transmitter circuitry checks ctsn before sending the next data byte. when ctsn is active, the transmitter sends the next byte. to stop the transmitter from sending the following byte, ctsn must be de-asserted before the midd le of the last stop bit that is currently being sent. the auto-cts function reduces interrup ts to the host system. when flow control is enabled, ctsn level changes do not trigger host interrupts because the device automatically controls its own transmitter. without auto-cts , the transmitter sends any data present in the transmit fifo and a receiver overrun error may result. 6.3 software flow control software flow control is enabled through the enhanced feature register and the modem control register. different combinations of software flow control can be enabled by setting different combinations of efr[3:0]. ta b l e 4 shows software flow control options. when ctsn is low, the transmitter keeps sending serial data out. when ctsn goes high before the middle of the last stop bit of t he current byte, the transmitter finishes sending the current byte, but is does not send the next byte. when ctsn goes from high to low, the tr ansmitter begins sending data again. fig 6. ctsn functional timing start byte 0 to 7 stop txn ctsn 002aaa22 7 start byte 0 to 7 stop table 4. software flow co ntrol options (efr[3:0]) efr[3] efr[2] efr[1] efr[0] tx, rx software flow controls 0 0 x x no transmit flow control 1 0 x x transmit xon1, xoff1 0 1 x x transmit xon2, xoff2 1 1 x x transmit xon1, xon2, xoff1, xoff2 x x 0 0 no receive flow control x x 1 0 receiver compared xon1, xoff1 x x 0 1 receiver compares xon2, xoff2 1 0 1 1 transmit xon1, xoff1 receiver compares xon1 and xon2, xoff1 and xoff2 0 1 1 1 transmit xon2, xoff2 receiver compares xon1 and xon2, xoff1 and xoff2 1 1 1 1 transmit xon1, xon2, xoff1, xoff2 receiver compares xon1 and xon2, xoff1 and xoff2
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 10 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos there are two other enhanced features relating to software flow control: ? xon any function (mcr[5]): operation will resume afte r receiving any character after recognizing the xoff character. it is possible that an xon1 character is recognized as an xon any character, which could cause an xon2 character to be written to the rx fifo. ? special character (efr[5]): incoming data is compared to xoff2. dete ction of the special character sets the xoff interrupt (i ir[4]) but does not ha lt transmission. the xoff interrupt is cleared by a read of the iir. the special character is transferred to the rx fifo. 6.3.1 receive flow control when software flow control operation is enabled, the sc 68c752b will compare incoming data with xoff1/xoff2 programmed characters (in certain cases, xoff1 and xoff2 must be received sequentially). when the correct xoff character are received, transmission is halted after completing transmission of the cu rrent character. xoff detection also sets iir[4] (if enabled via ier[5]) and causes irq to go high. to resume transmission, an xon1/xon2 char acter must be received (in certain cases xon1 and xon2 must be received sequentially). when the correct xon characters are received, iir[4] is cleared, and the xoff interrupt disappears. 6.3.2 transmit flow control xoff1/xoff2 character is transmitted when the rx fifo has passed the halt trigger level programmed in tcr[3:0]. xon1/xon2 character is transmitted when the rx fifo reaches the resume trigger level programmed in tcr[7:4]. the transmission of xoff/xon(s) follows the exact same protocol as transmission of an ordinary byte from the fifo. this means that even if the word length is set to be 5, 6, or 7 characters, then the 5, 6, or 7 least signif icant bits of xoff1/xo ff2, xon1/xon2 will be transmitted. (note that the transmission of 5, 6, or 7 bits of a character is seldom done, but this functionality is inclu ded to maintain compatib ility with earlier designs.) it is assumed that software flow control and hardware flow control will never be enabled simultaneously. figure 7 shows an example of software flow control.
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 11 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6.3.3 software flow control example 6.3.3.1 assumptions uart1 is transmitting a large text file to uart2. both uarts are using software flow control with single character xoff (0f) and xon (0d) tokens. both have xoff threshold (tcr[3:0] = f) set to 60, and xon threshold (tcr[7:4] = 8) set to 32. both have the interrupt receive threshold (tlr[7:4] = d) set to 52. uart1 begins transmission and sends 52 characters, at which point uart2 will generate an interrupt to its processor to service the rx fifo, but assu me the interrupt latency is fairly long. uart1 will continue sending charac ters until a total of 60 characters have been sent. at this time, uart2 will transmit a 0fh to uart1, informing uart1 to halt transmission. uart1 will likely send the 61 st character while uart2 is sending the xoff character. now uart2 is serviced and the processor reads enough data out of the rx fifo that the level drops to 32. uart2 will now send a 0dh to uart1, informing uart1 to resume transmission. fig 7. software flow control example transmit fifo parallel-to-serial serial-to-parallel xon1 word xon2 word xoff1 word xoff2 word receive fifo parallel-to-serial serial-to-parallel xon1 word xon2 word xoff1 word xoff2 word uart2 uart1 002aaa22 9 data xoff?xon?xoff compare programmed xon-xoff characters
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 12 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6.4 reset ta b l e 5 summarizes the state of register after reset. remark: registers dll, dlm, spr, xon1, xon2, xoff1, xoff2 are not reset by the top-level reset signal reset , that is, they hold their in itialization values during reset. ta b l e 6 summarizes the state of registers after reset. table 5. register reset functions register reset control reset state interrupt enable register reset all bits cleared interrupt identific ation register reset bit 0 is set; all other bits cleared fifo control register reset all bits cleared line control register reset reset to 0001 1101 (1dh) modem control register reset all bits cleared line status register reset bits 5 and 6 set; all other bits cleared modem status register reset bits 0 to 3 cleared; bits 4 to 7 input signals enhanced featur e register reset all bits cleared receiver holding register reset pointer logic cleared transmitter holding register reset pointer logic cleared transmission control register reset all bits cleared trigger level register reset all bits cleared table 6. signal reset functions signal reset control reset state txn reset high rtsn reset high dtrn reset high rxrdyn reset high txrdyn reset low
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 13 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6.5 interrupts the sc68c752b has interrupt generation and prioritization (six prioritized levels of interrupts) capability. the interrupt enable register (ier) enables each of the six types of interrupts and the irq signal in response to an inte rrupt generation. the ier can also disable the interrupt system by clearing bits 3:0 and bits 7:5. when an interrupt is generated, the iir indicates that an interrupt is pending and provides the type of interrupt through iir[5:0]. ta b l e 7 summarizes the interrupt control functions. it is important to note that for the framing error, parity error, and break conditions, lsr[7] generates the interrupt. lsr[7] is set when there is an error anywhere in the rx fifo, and is cleared only when there are no more errors remaining in th e fifo. lsr[4:2] always represent the error status for the received character at the top of the rx fifo. reading the rx fifo updates lsr[4:2] to the appropriate status for the new character at the top of the fifo. if the rx fifo is empty, then lsr[4:2] are all zeros. for the xoff interrupt, if an xoff flow characte r detection caused the interrupt, the interrupt is cleared by an xon flow character detectio n. if a special character detection caused the interrupt, the interrupt is cl eared by a read of the iir. table 7. interrupt control functions iir[5:0] priority level interrupt type interrupt source interrupt reset method 000001 none none none none 000110 1 receiver line status oe, fe, pe, or bi errors occur in characters in the rx fifo fe, pe, bi: all erroneous characters are read from the rx fifo. oe: read lsr 001100 2 rx time-out stale data in rx fifo read rhr 000100 2 rhr interrupt drdy (data ready) (fifo disable) rx fifo above trigger level (fifo enable) read rhr 000010 3 thr interrupt tfe (thr empty) (fifo disable) tx fifo passes above trigger level (fifo enable) read iir or a write to the thr 000000 4 modem status msr[3:0] = 0 read msr 010000 5 xoff interrupt receive xoff character(s)/ special character receive xon character(s)/ read of iir 100000 6 cts, rts rtsn pin or ctsn pin change state from active (low) to inactive (high) read iir
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 14 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6.5.1 interrupt mode operation in interrupt mode (if any bit of ier[3:0] is 1) the processor is informed of the status of the receiver and transmitter by an interrupt signal, irq . therefore, it is not necessary to continuously poll the line status register (lsr) to see if any interrupt needs to be serviced. figure 8 shows interrupt mode operation. 6.5.2 polled mode operation in polled mode (ier[3:0] = 0000) the status of the receiver and transmitter can be checked by polling the line status register (lsr ). this mode is an alternative to the fifo interrupt mode of operation where the status of the receiver and transmitter is automatically known by means of interrupts sent to the cpu. figure 9 shows fifo polled mode operation. fig 8. interrupt mode operation 11 11 iir ier thr rhr processor r/w irq 002aab09 6 fig 9. fifo polled mode operation 00 00 iir ier thr rhr processor r/w 002aab09 7
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 15 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6.6 dma operation there are two modes of dma operation, dma mode 0 or dma mode 1, selected by fcr[3]. in dma mode 0 or fifo disable (fcr[0] = 0) dma occurs in single character transfers. in dma mode 1, multi-character (or block) dma transfers are managed to relieve the processor for longer periods of time. 6.6.1 single dma transfers (dma mode 0/fifo disable) figure 10 shows txrdyn and rxrdyn in dma mode 0/fifo disable. 6.6.1.1 transmitter when empty, the txrdyn signal becomes active. txrdyn will go inactive after one character has been loaded into it. 6.6.1.2 receiver rxrdyn is active when there is at least one character in the fifo. it becomes inactive when the receiver is empty. fig 10. txrdyn and rxrdyn in dma mode 0/fifo disable transmit wrptr wrptr fifo empty txrdyn receive rdptr rdptr fifo empty rxrdyn rxrdyn 002aaa232 at least one location filled at least one location filled txrdyn
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 16 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6.6.2 block dma transfers (dma mode 1) figure 11 shows txrdyn and rxrdyn in dma mode 1. 6.6.2.1 transmitter txrdyn is active when there is a trigger leve l number of spaces available. it becomes inactive when the fifo is full. 6.6.2.2 receiver rxrdyn becomes active when the trigger level has been reached, or when a time-out interrupt occurs. it will go inactive when the fifo is empty or an error in the receive fifo is flagged by lsr[7]. 6.7 sleep mode sleep mode is an enhanced feature of the sc68c752b uart. it is enabled when efr[4], the enhanced functions bit, is set and when ier[4] is set. sleep mode is entered when: ? the serial data input line, rxn, is idle (see section 6.8 ? break and time-out conditions ? ). ? the transmit fifo and transm it shift register are empty. ? there are no interrupts pending except thr and time-out interrupts. remark: sleep mode will not be entered if there is data in the receive fifo. in sleep mode, the uart clock and baud rate clock are stopped. since most registers are clocked using these clocks, th e power consumption is greatly reduced. the uart will wake up when any change is detected on the rxn line, when there is any change in the state of the modem input pins, or if data is written to the transmit fifo. remark: writing to the divisor latches, dll and dl m, to set the baud clock, must not be done during sleep mode. therefore, it is adv isable to disable sleep mode using ier[4] before writing to dll or dlm. fig 11. txrdyn and rxrdyn in dma mode 1 transmit wrptr wrptr txrdyn fifo full txrdyn receive rdptr rdptr fifo empty rxrdyn rxrdyn 002aaa234 trigger level trigger level at least one location filled
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 17 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 6.8 break and time-out conditions an rx idle condition is detected when th e receiver line, rxn, has been high for 4 character time. the receiver line is sampled midway through each bit. when a break condition occurs, the txn line is pulled low. a break condition is activated by setting lcr[6]. 6.9 programmable baud rate generator the sc68c752b uart contains a programmable baud generator that takes any clock input and divides it by a divisor in the range between 1 and (2 16 ? 1). an additional divide-by-4 prescaler is also available and can be selected by mcr[7], as shown in figure 12 . the output frequency of the baud rate generator is 16 times the baud rate. the formula for the divisor is: (1) where: prescaler = 1, when mcr[7] is set to 0 after reset (divide-by -1 clock selected) prescaler = 4, when mcr[7] is set to 1 after reset (divide-by -4 clock selected). remark: the default value of prescaler after reset is divide-by-1. figure 12 shows the internal prescaler and baud rate generator circuitry. dll and dlm must be written to in order to program the baud rate. dll and dlm are the least significant and most sign ificant byte of the baud rate divisor. if dll and dlm are both zero, the uart is effectively disa bled, as no baud cl ock will be generated. remark: the programmable baud rate generator is provided to select both the transmit and receive clock rates. ta b l e 8 and ta b l e 9 show the baud rate and divisor correlation for crystal with frequency 1.8432 mhz and 3.072 mhz, respectively. figure 13 shows the crystal clock circuit reference. fig 12. prescaler and baud rate generator block diagram divisor xtal1 crystal input frequency prescaler ----------------------------------------------------------------------------------- ?? ?? desired baud rate 16 ----------------------------------------------------------------------------------------- = baud rate generator logic mcr[7] = 1 mcr[7] = 0 prescaler logic (divide-by-1) internal oscillator logic 002aaa233 xtal1 xtal2 input clock prescaler logic (divide-by-4) reference clock internal baud rate clock for transmitter and receiver
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 18 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos table 8. baud rates using a 1.8432 mhz crystal desired baud rate divisor used to generate 16 clock percent error difference between desired and actual 50 2304 75 1536 110 1047 0.026 134.5 857 0.058 150 768 300 384 600 192 1200 96 1800 64 2000 58 0.69 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 56000 2 2.86 table 9. baud rates using a 3.072 mhz crystal desired baud rate divisor used to generate 16 clock percent error difference between desired and actual 50 2304 75 2560 110 1745 0.026 134.5 1428 0.034 150 1280 300 640 600 320 1200 160 1800 107 0.312 2000 96 2400 80 3600 53 0.628 4800 40 7200 27 1.23 9600 20 19200 10 38400 5
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 19 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 7. register descriptions each register is selected using address lines a0, a1, a2, and in some cases, bits from other registers. the programming combinations for register selection are shown in ta b l e 1 0 . [1] mcr[7] can only be modified when efr[4] is set. [2] accessed by a combination of address pins and register bits. [3] accessible only wh en lcr[7] is logic 1. [4] accessible only when lcr is set to 1011 1111 (bfh). [5] accessible only when efr[4] = 1 and mcr[6] = 1, t hat is, efr[4] and mcr[6] are read/write enables. [6] accessible only when cs = 0, mcr[2] = 1, and loopback is disabled (mcr[4] = 0). fig 13. crystal oscillator connections 002aaa87 0 c2 47 pf xtal1 xtal2 x1 1.8432 mhz c1 22 pf c2 33 pf xtal1 xtal2 1.5 k x1 1.8432 mhz c1 22 pf table 10. register map - read/write properties a2 a1 a0 read mode write mode 0 0 0 receive holding register (rhr) transmit holding register (thr) 0 0 1 interrupt enable register (ier) interrupt enable register 0 1 0 interrupt identification register (iir) fifo control register (fcr) 0 1 1 line control register (lcr) line control register 1 0 0 modem control register (mcr) [1] modem control register [1] 1 0 1 line status register (lsr) 1 1 0 modem status register (msr) 1 1 1 scratchpad register (spr) scratchpad register 0 0 0 divisor latch lsb (dll) [2] [3] divisor latch lsb [2] [3] 0 0 1 divisor latch msb (dlm) [2] [3] divisor latch msb [2] [3] 0 1 0 enhanced feature register (efr) [2] [4] enhanced feature register [2] [4] 100xon1 word [2] [4] xon1 word [2] [4] 101xon2 word [2] [4] xon2 word [2] [4] 110xoff1 word [2] [4] xoff1 word [2] [4] 111xoff2 word [2] [4] xoff2 word [2] [4] 1 1 0 transmission control register (tcr) [2] [5] transmission control register [2] [5] 1 1 1 trigger level register (tlr) [2] [5] trigger level register [2] [5] 1 1 1 fifo ready register [2] [6]
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 20 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos ta b l e 11 lists and describes the sc68c752b internal registers. [1] these registers are accessible only when lcr[7] = 0. [2] this bit can only be modified if register bit efr[4] is enabled, that is, if enhanced functions are enabled. [3] the special register set is accessibl e only when lcr[7] is set to a logic 1. [4] enhanced feature register; xon1/xon2 and xoff1/xoff2 are accessible only when lcr is set to ?bfh?. table 11. sc68c752b internal registers a2 a1 a0 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/ write general register set [1] 0 0 0 rhr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r 0 0 0 thr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 001ier cts interrupt enable [2] rts interrupt enable [2] xoff [2] sleep mode [2] modem status interrupt receive line status interrupt thr empty interrupt rx data available interrupt r/w 0 1 0 fcr rx trigger level (msb) rx trigger level (lsb) tx trigger level (msb) [2] tx trigger level (lsb) [2] dma mode select tx fifo reset rx fifo reset fifo enable w 0 1 0 iir fcr[0] fcr[0] cts , rts xoff interrupt priority bit 2 interrupt priority bit 1 interrupt priority bit 0 interrupt status r 011lcr dlab break control bit set parity parity type select parity enable number of stop bits word length bit 1 word length bit 0 r/w 100mcr 1 or 1 /4 clock [2] tcr and tlr enable [2] xon any [2] enable loopback opa / opb control fifo ready enable rts dtr r/w 1 0 1 lsr error in rx fifo thr and tsr empty thr empty break interrupt framing error parity error overrun error data in receiver r 1 1 0 msr cd ri dsr cts cd ri dsr cts r 1 1 1 spr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 1 1 0 tcr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 1 1 1 tlr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 111fifo rdy0 0 rx fifo b status rx fifo a status 0 0 tx fifo b status tx fifo a status r special register set [3] 0 0 0 dll bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 0 0 1 dlm bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w enhanced register set [4] 010efr auto-cts auto-rts special character detect enable enhanced functions [2] software flow control bit 3 software flow control bit 2 software flow control bit 1 software flow control bit 0 r/w 1 0 0 xon1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 1 0 1 xon2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 1 1 0 xoff1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w 1 1 1 xoff2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 21 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos remark: refer to the notes under ta b l e 1 0 for more register access information. 7.1 receiver holding register (rhr) the receiver section consists of the receiv er holding register (rhr) and the receiver shift register (rsr). the rhr is actually a 64-byte fifo. the rsr receives serial data from the rx terminal. the data is converted to parallel data and moved to the rhr. the receiver section is controlled by the line control register. if the fifo is disabled, location zero of the fifo is used to store the characters. remark: in this case, characters are overwritten if overflow occurs. if overflow occurs, characters are lost. th e rhr also stores the error status bits associated with each character. 7.2 transmit holdin g register (thr) the transmitter section consists of the transm it holding register (thr) and the transmit shift register (tsr). the thr is actually a 64-byte fifo. the thr receives data and shifts it into the tsr, where it is converted to serial data and moved out on the tx terminal. if the fifo is disabled, the fifo is still used to store the byte. characters are lost if overflow occurs.
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 22 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 7.3 fifo control register (fcr) this is a write-only register that is used fo r enabling the fifos, clearing the fifos, setting transmitter and receiver tr igger levels, and selecting the type of dma signalling. table 12 shows fifo control register bit settings. table 12. fifo control register bits description bit symbol description 7:6 fcr[7] (msb), fcr[6] (lsb) rx trigger. sets the trigger level for the receive fifo. 00 - 8 characters 01 - 16 characters 10 - 56 characters 11 - 60 characters 5:4 fcr[5] (msb), fcr[4] (lsb) tx trigger. sets the trigger level for the transmit fifo. 00 - 8 spaces 01 - 16 spaces 10 - 32 spaces 11 - 56 spaces fcr[5:4] can only be modified and enabled when efr[4] is set. this is because the transmit trigger level is regarded as an enhanced function. 3 fcr[3] dma mode select. logic 0 = set dma mode ?0? logic 1 = set dma mode ?1? 2 fcr[2] reset transmit fifo. logic 0 = no fifo transmit reset (normal default condition) logic 1 = clears the contents of the transmit fifo and resets the fifo counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. 1 fcr[1] reset receive fifo. logic 0 = no fifo receive reset (normal default condition) logic 1 = clears the contents of the receive fifo and resets the fifo counter logic (the receive shift register is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. 0 fcr[0] fifo enable. logic 0 = disable the transmit and receive fifo (normal default condition) logic 1 = enable the transmit and receive fifo
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 23 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 7.4 line control register (lcr) this register controls the data communication format. the word length, number of stop bits, and parity type are selected by wr iting the appropriate bits to the lcr. table 13 shows the line control register bit settings. table 13. line control register bits description bit symbol description 7 lcr[7] divisor latch enable. logic 0 = divisor latch disabled (normal default condition) logic 1 = divisor latch enabled 6 lcr[6] break control bit. when enabled , the break control bit causes a break condition to be transmitted (the txn output is forced to a logic 0 state). this condition exists until disabled by setting lcr[6] to a logic 0. logic 0 = no break condition (normal default condition) logic 1 = forces the transmitter output (txn) to a logic 0 to alert the communication terminal to a line break condition 5 lcr[5] set parity. lcr[5] selects th e forced parity format (if lcr[3] = 1). logic 0 = parity is not forced (normal default condition) lcr[5] = logic 1 and lcr[4] = logic 0: parity bit is forced to a logic 1 for the transmit and receive data. lcr[5] = logic 1 and lcr[4] = logic 1: parity bit is forced to a logic 0 for the transmit and receive data. 4 lcr[4] parity type select. logic 0 = odd parity is generated (if lcr[3] = 1). logic 1 = even parity is generated (if lcr[3] = 1). 3 lcr[3] parity enable. logic 0 = no parity (normal default condition). logic 1 = a parity bit is generated during transmission and the receiver checks for received parity. 2 lcr[2] number of stop bits. specifies the number of stop bits. 0 = 1 stop bit (word length = 5, 6, 7, 8) 1 = 1.5 stop bits (word length = 5) 1 = 2 stop bits (word length = 6, 7, 8) 1:0 lcr[1:0] word length bits 1, 0. these tw o bits specify the word length to be transmitted or received. 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 24 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 7.5 line status register (lsr) ta b l e 1 4 shows the line status register bit settings. when the lsr is read, lsr[4:2] reflect the erro r bits (bi, fe, pe) of the character at the top of the receive fifo (next character to be read). the lsr[4:2] registers do not physically exist, as the data read from the re ceive fifo is output directly onto the output data bus, d[4:2], when the lsr is read. theref ore, errors in a character are identified by reading the lsr and then reading the rhr. lsr[7] is set when there is an error anywhere in the receive fifo, and is cleared only when there are no more errors remaining in the fifo. reading the lsr does not cause an incremen t of the receive fifo read pointer. the receive fifo read pointer is incremented by reading the rhr. table 14. line status register bits description bit symbol description 7 lsr[7] fifo data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error, or break indication is in the receiver fifo. this bit is cleared when no more errors are present in the fifo. 6 lsr[6] thr and tsr empty. this bit is the transmit empty indicator. logic 0 = transmitter hold and shift registers are not empty logic 1 = transmitter hold and shift registers are empty 5 lsr[5] thr empty. this bit is the transmit holding register empty indicator. logic 0 = transmit hold register is not empty logic 1 = transmit hold register is empty. the processor can now load up to 64 bytes of data into the thr if the tx fifo is enabled. 4 lsr[4] break interrupt. logic 0 = no break condition (normal default condition) logic 1 = a break condition occurred and associated byte is 00, that is, rxn was low for one character time frame. 3 lsr[3] framing error. logic 0 = no framing error in data being read from receive fifo (normal default condition) logic 1 = framing error occurred in data being read from receive fifo, that is, received data did not have a valid stop bit. 2lsr[2]parity error. logic 0 = no parity error (normal default condition) logic 1 = parity error in data being read from receive fifo 1 lsr[1] overrun error. logic 0 = no overrun error (normal default condition) logic 1 = overrun error has occurred 0 lsr[0] data in receiver. logic 0 = no data in receive fifo (normal default condition) logic 1 = at least one character in the receive fifo
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 25 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos remark: the three error bits (parity, framing, break) may not be updated correctly in the first read of the lsr when the input clock (xtal1) is running faster than 36 mhz. however, the second read is always correct. it is strongly recommended that when using this device with a clock faster than 36 mhz, that the lsr be read twice and only the second read be used for decision making. all other bits in the lsr are correct on all reads. 7.6 modem control register (mcr) the mcr controls the interface with the mode, data set, or peripheral device that is emulating the modem. table 15 shows modem control register bit settings. [1] mcr[7:5] can only be modified when efr[4] is set, that is, efr[4] is a write enable. table 15. modem control register bits description bit symbol description 7 mcr[7] [1] clock select. logic 0 = divide-by-1 clock input logic 1 = divide-by-4 clock input 6 mcr[6] [1] tcr and tlr enable. logic 0 = no action. logic 1 = enable access to the tcr and tlr registers 5 mcr[5] [1] xon any. logic 0 = disable xon any function logic 1 = enable xon any function 4 mcr[4] enable loopback. logic 0 = normal operating mode logic 1 = enable local loopback mode (internal). in this mode the mcr[3:0] signals are looped back into msr[7:4] and the txn output is looped back to the rxn input internally. 3 mcr[3] opa /opb control. logic 0 = forces opa /opb output to high state logic 1 = forces opa /opb output to low state. in loopback mode, controls msr[7]. 2 mcr[2] fifo ready enable. logic 0 = disable the fifo rdy register logic 1 = enable the fifo rdy register. in loopback mode, controls msr[6]. 1 mcr[1] rts logic 0 = force rtsn output to inactive (high) logic 1 = force rtsn output to active (low). in loopback mode, controls msr[4]. if auto-rts is enabled, the rtsn output is controlled by hardware flow control. 0 mcr[0] dtr logic 0 = force dtrn output to inactive (high) logic 1 = force dtrn output to active (low). in loopback mode, controls msr[5].
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 26 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 7.7 modem status register (msr) this 8-bit register provides information about the current state of the control lines from the mode, data set, or peripheral device to the processor. it also indicates when a control input from the modem changes state. ta b l e 1 6 shows modem status register bit settings per channel. [1] the primary inputs rin , cdn , ctsn , dsrn are all active low, but their r egistered equivalents in the msr and mcr (in loopback mode) registers are active high. table 16. modem status regi ster bits description bit symbol description 7msr[7] [1] cd (active high, logic 1). this bit is the complement of the cdn input during normal mode. during internal loopback mode, it is equivalent to the state of mcr[3]. 6msr[6] [1] ri (active high, logic 1). this bi t is the complement of the rin input during normal mode. during internal loopback mode, it is equivalent to the state of mcr[2]. 5msr[5] [1] dsr (active high, logic 1). this bi t is the complement of the dsrn input during normal mode. during internal loopback mode, it is equivalent to the state of mcr[0]. 4msr[4] [1] cts (active high, logic 1). this bit is the complement of the ctsn input during normal mode. during internal loopback mode, it is equivalent to the state of mcr[1]. 3msr[3] cd. indicates that cdn input (or mcr[3] in loopback mode) has changed state. cleared on a read. 2msr[2] ri. indicates that rin input (or mcr[2] in loopback mode) has changed state from low to high. cleared on a read. 1msr[1] dsr. indicates that dsrn input (or mcr[0] in loopback mode) has changed state. cleared on a read. 0msr[0] cts. indicates that ctsn input (or mcr[1] in loopback mode) has changed state. cleared on a read.
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 27 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 7.8 interrupt enable register (ier) the interrupt enable register (ier) enables each of the six types of interrupt, receiver error, rhr interrupt, thr interrupt, xoff received, or ctsn /rtsn change of state from low to high. the irq output signal is activated in re sponse to interrupt generation. ta b l e 1 7 shows interrupt enable register bit settings. [1] ier[7:4] can only be modified if efr[4] is set, that is , efr[4] is a write enable. re-enabling ier[1] will not cause a new interrupt if the thr is below the threshold. table 17. interrupt enable register bits description bit symbol description 7ier[7] [1] cts interrupt enable. logic 0 = disable the cts interrupt (normal default condition) logic 1 = enable the cts interrupt 6ier[6] [1] rts interrupt enable. logic 0 = disable the rts interrupt (normal default condition) logic 1 = enable the rts interrupt 5ier[5] [1] xoff interrupt. logic 0 = disable the xoff interrupt (normal default condition) logic 1 = enable the xoff interrupt 4ier[4] [1] sleep mode. logic 0 = disable sleep mode (normal default condition) logic 1 = enable sleep mode. see section 6.7 ? sleep mode ? for details. 3 ier[3] modem status interrupt. logic 0 = disable the modem status register interrupt (normal default condition) logic 1 = enable the modem status register interrupt 2 ier[2] receive line status interrupt. logic 0 = disable the receiver line status interrupt (normal default condition) logic 1 = enable the receiver line status interrupt 1 ier[1] transmit holding register interrupt. logic 0 = disable the thr interrupt (normal default condition) logic 1 = enable the thr interrupt 0 ier[0] receive holding register interrupt. logic 0 = disable the rhr interrupt (normal default condition) logic 1 = enable the rhr interrupt
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 28 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 7.9 interrupt identification register (iir) the iir is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. ta b l e 1 8 shows interrupt identificat ion register bit settings. the interrupt priority list is shown in ta b l e 1 9 . table 18. interrupt identification register bits description bit symbol description 7:6 iir[7:6] mirror the contents of fcr[0]. 5 iir[5] rtsn /ctsn low-to-high change of state 4 iir[4] 1 = xoff/special character has been detected 3:1 iir[3:1] 3-bit encoded interrupt. see table 19 . 0 iir[0] interrupt status. logic 0 = an interrupt is pending logic 1 = no interrupt is pending table 19. interrupt priority list priority level iir[5] iir[4] iir[3] iir[2] iir[1] iir[0] source of the interrupt 1 000110receiver line status error 2 001100receiver time-out interrupt 2 000100rhr interrupt 3 000010thr interrupt 4 000000modem interrupt 5 010000received xoff signal/ special character 6 100000ctsn , rtsn change of state from active (low) to inactive (high)
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 29 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 7.10 enhanced featur e register (efr) this 8-bit register enables or disabl es the enhanced feat ures of the uart. ta b l e 2 0 shows the enhanced feature register bit settings. 7.11 divisor latches (dll, dlm) these are two 8-bit registers which store the 16- bit divisor for generation of the baud clock in the baud rate generator. dlm stores the most significant part of the divisor. dll stores the least significant part of the divisor. note that dll and dlm can only be written to before sleep mode is enabled, that is, before ier[4] is set. 7.12 transmission control register (tcr) this 8-bit register is used to store the re ceive fifo threshold le vels to stop/start transmission during hardware/software flow control. ta b l e 2 1 shows transmission control register bit settings. tcr trigger levels are available from 0 byt es to 60 bytes with a granularity of four. table 20. enhanced feature register bits description bit symbol description 7 efr[7] cts flow control enable. logic 0 = cts flow control is disabled (normal default condition) logic 1 = cts flow control is enabled. transmission will stop when a high signal is detected on the ctsn pin. 6efr[6]rts flow control enable. logic 0 = rts flow control is disabled (normal default condition) logic 1 = rts flow control is enabled. the rtsn pin goes high when the receiver fifo halt trigger level tcr[3:0] is reached, and goes low when the receiver fifo resume transmission trigger level tcr[7:4] is reached. 5 efr[5] special character detect. logic 0 = special character detect disabled (normal default condition) logic 1 = special character detect enab led. received data is compared with xoff2 data. if a match occurs, the rece ived data is transferred to fifo and iir[4] is set to a logic 1 to indicate a special character has been detected. 4 efr[4] enhanced functions enable bit. logic 0 = disables enhanced functions and writing to ier[7:4], fcr[5:4], mcr[7:5] logic 1 = enables the enhanced function ier[7:4], fcr[5:4], and mcr[7:5] can be modified, that is, this bit is therefore a write enable 3:0 efr[3:0] combinations of software flow c ontrol can be selected by programming these bits. see table 4 ? software flow control options (efr[3:0]) ? on page 9 . table 21. transmission control register bits description bit symbol description 7:4 tcr[7:4] receive fifo trigger level to resume transmission (0 bytes to 60 bytes). 3:0 tcr[3:0] receive fifo trigger level to halt transmission (0 bytes to 60 bytes).
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 30 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos remark: tcr can only be written to when efr[4] = 1 and mcr[6] = 1. the programmer must program the tcr such that tcr[3:0] > tcr[7:4]. there is no built-in hardware check to make sure th is condition is met. also, the tc r must be programmed with this condition before auto-rts or software flow control is enabled to avoid spurious operation of the device. 7.13 trigger level register (tlr) this 8-bit register is pulsed to store the transmit and received fifo trigger levels used for dma and interrupt generation. trigger levels from 4 to 60 can be programmed with a granularity of 4. ta b l e 2 2 shows trigger level register bit settings. remark: tlr can only be written to when efr[4] = 1 and mcr[6] = 1. if tlr[3:0] or tlr[7:4] are logic 0, the selectable trigger levels via the fifo control register (fcr) are used for the transmit and receive fifo trigger levels. tr igger levels from 4 bytes to 60 bytes are available with a granularity of four. the tlr should be programmed for n ? 4 , where n is the desired trigger level. when the trigger level setting in tlr is zero, the sc68c752b us es the trigger level setting defined in fcr. if tlr has non- zero trigger level value, the tr igger level defined in fcr is discarded. this applies to both transmit fifo and receive fifo trigger level setting. when tlr is used for rx trigger level control, fcr[7:6] should be left at the default state, that is, ?00?. 7.14 fifo ready register the fifo ready register provides real-time st atus of the transmit and receive fifos of both channels. the fifo rdy register is a read-only register that can be accessed when any of the two uarts is selected cs = 0, mcr[2] (fifo rdy enable) is a logic 1, and loopback is disabled. the address is 111. table 22. trigger level register bits description bit symbol description 7:4 tlr[7:4] receive fifo trigger levels (4 to 60), number of characters available. 3:0 tlr[3:0] transmit fifo trigger levels (4 to 60), number of spaces available. table 23. fifo ready register bits description bit symbol description 7:6 fifo rdy[7:6] unused; always 0 5 fifo rdy[5] receive fifo b status; related to dma 4 fifo rdy[4] receive fifo a status; related to dma 3:2 fifo rdy[3:2] unused; always 0 1 fifo rdy[1] transmit fifo b status; related to dma 0 fifo rdy[0] transmit fifo a status; related to dma
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 31 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 8. programmer?s guide the base set of registers that is used during high-speed data transfer have a straightforward access method. the extended function registers require special access bits to be decoded along wit h the address lines. the fo llowing guide will help with programming these registers. note that the de scriptions below are for individual register access. some streamlining through interleaving can be obtained when programming all the registers. table 24. register programming guide command actions set baud rate to value1, value2 read lcr (03h), save in temp set lcr (03h) to 80h set dll (00h) to value1 set dlm (01h) to value2 set lcr (03h) to temp set xoff1, xon1 to va lue1, value2 read lcr (03h), save in temp set lcr (03h) to bfh set xoff1 (06h) to value1 set xon1 (04h) to value2 set lcr (03h) to temp set xoff2, xon2 to va lue1, value2 read lcr (03h), save in temp set lcr (03h) to bfh set xoff2 (07h) to value1 set xon2 (05h) to value2 set lcr (03h) to temp set software flow control mode to value read lcr (03h), save in temp set lcr (03h) to bfh set efr (02h) to value set lcr (03h) to temp set flow control threshold to value read lcr (03h), save in temp1 set lcr (03h) to bfh read efr (02h), save in temp2 set efr (02h) to 10h + temp2 set lcr (03h) to 00h read mcr (04h), save in temp3 set mcr (04h) to 40h + temp3 set tcr (06h) to value set mcr (04h) to temp3 set lcr (03h) to bfh set efr (02h) to temp2 set lcr (03h) to temp1
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 32 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos [1] sign here means bit-and. set tx fifo and rx fifo thresholds to value read lcr (03h), save in temp1 set lcr (03h) to bfh read efr (02h), save in temp2 set efr (02h) to 10h + temp2 set lcr (03h) to 00h read mcr (04h), save in temp3 set mcr (04h) to 40h + temp3 set tlr (07h) to value set mcr (04h) to temp3 set lcr (03h) to bfh set efr (02h) to temp2 set lcr (03h) to temp1 read fifo rdy register read mcr (04h), save in temp1 set temp2 = temp1 efh [1] set mcr (04h) = 40h + temp2 read ffr (07h), save in temp2 pass temp2 back to host set mcr (04h) to temp1 set prescaler value to divide-by- 1 read lcr (03h), save in temp1 set lcr (03h) to bfh read efr (02h), save in temp2 set efr (02h) to 10h + temp2 set lcr (03h) to 00h read mcr (04h), save in temp3 set mcr (04h) to temp3 7fh [1] set lcr (03h) to bfh set efr (02h) to temp2 set lcr (03h) to temp1 set prescaler value to divide-by- 4 read lcr (03h), save in temp1 set lcr (03h) to bfh read efr (02h), save in temp2 set efr (02h) to 10h + temp2 set lcr (03h) to 00h read mcr (04h), save in temp3 set mcr (04h) to temp3 + 80h set lcr (03h) to bfh set efr (02h) to temp2 set lcr (03h) to temp1 table 24. register programming guide ?continued command actions
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 33 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 9. limiting values table 25. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage - 7 v v n voltage on any other pin at d7 to d0 gnd ? 0.3 v cc +0.3 v at any input only pin gnd ? 0.3 5.3 v v o output voltage ? 0.3 v cc +0.3 v t amb ambient temperature operating in free-air ? 40 +85 c t stg storage temperature ? 65 +150 c
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 34 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 10. static characteristics [1] meets ttl levels, v il(min) = 2 v and v ih(max) = 0.8 v on non-hysteresis inputs. [2] applies for external output buffers. [3] these parameters apply for d[7:0]. [4] these parameters apply for dtra , dtrb , rtsa , rtsb , rxrdya , rxrdyb , txrdya , txrdyb , txa, txb. [5] except xtal2, v ol =1v typical. [6] these junction temperatures refl ect simulated conditions. absolute maximum junction temperature is 150 c. the customer is responsible for verifyi ng junction temperature. [7] applies to external clock; crystal oscillator max. 24 mhz. [8] measurement condition, normal operation other than sleep mode: v cc = 3.3 v; t amb =25 c. full duplex serial activity on all two serial (uart) channels at the clock frequency specified in the recommended operating conditi ons with divisor of 1. table 26. static characteristics tolerance of v cc = 10 %. symbol parameter conditions v cc =2.5v v cc =3.3v and 5v unit min typ max min typ max v cc supply voltage v cc ? 10 % v cc v cc +10% v cc ? 10 % v cc v cc +10% v v i input voltage 0 - v cc 0-v cc v v ih high-level input voltage [1] 1.6 - v cc 2.0 - v cc v v il low-level input voltage [1] - - 0.65 - - 0.8 v v o output voltage [2] 0-v cc 0-v cc v v oh high-level output voltage i oh = ? 8ma [3] --- 2.0--v i oh = ? 4ma [4] --- 2.0--v i oh = ? 800 a [3] 1.85 - - - - - v i oh = ? 400 a [4] 1.85 - - - - - v v ol low-level output voltage i ol =8ma [3] [5] --- --0.4v i ol =4ma [4] [5] --- --0.4v i ol =2ma [3] [5] --0.4 ---v i ol =1.6ma [4] [5] --0.4 ---v c i input capacitance - - 18 - - 18 pf t amb ambient temperature operating ? 40 +25 +85 ? 40 +25 +85 c t j junction temperature [6] 0 +25 +125 0 +25 +125 c f xtal1 frequency on pin xtal1 [7] - - 50 - - 80 mhz clock duty cycle - 50 - - 50 - % i cc supply current f = 5 mhz [8] --3.5 --4.5ma i cc(sleep) sleep mode supply current - - 200 - - 200 a
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 35 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 11. dynamic characteristics [1] rclk is an internal signal derived from divisor latch lsb (dll) and divisor latch msb (dlm) divisor latches. [2] applies to external clock; crystal oscillator max 24 mhz. [3] maximum frequency = [4] reset pulse must occur when cs is inactive. table 27. dynamic characteristics t amb = ? 40 c to +85 c; tolerance of v cc 10 %, unless specified otherwise. symbol parameter conditions v cc =2.5v v cc =3.3v and 5v unit min max min max t d1 r/w to chip select 10 - 10 - ns t d2 read cycle delay 25 pf load 20 - 20 - ns t d3 delay from cs to data 25 pf load - 77 - 26 ns t d4 data disable time 25 pf load - 15 - 15 ns t d6 write cycle delay 25 - 25 - ns t d7 delay from write to output 25 pf load - 100 - 33 ns t d8 delay to set interrupt from modem input 25 pf load - 100 - 24 ns t d9 delay to reset interrupt fr om read 25 pf load - 100 - 24 ns t d10 delay from stop to set interrupt - 1t rclk [1] -1t rclk [1] s t d11 delay from read to reset interrupt 25 pf load - 100 - 29 ns t d12 delay from start to set interrupt - 100 - 100 ns t d13 delay from write to transmit start 8t rclk [1] 24t rclk [1] 8t rclk [1] 24t rclk [1] s t d14 delay from write to reset interrupt - 100 - 70 ns t d15 delay from stop to set rxrdy -1t rclk [1] -1t rclk [1] s t d16 delay from read to reset rxrdy - 100 - 75 ns t d17 delay from write to set txrdy - 100 - 70 ns t d18 delay from start to reset txrdy -16t rclk [1] - 16t rclk [1] s t h2 r/w hold time from cs 10 - 10 - ns t h3 data hold time 15 - 15 - ns t h4 address hold time 15 - 15 - ns t wl pulse width low 10 - 6 - ns t wh pulse width high 10 - 6 - ns f xtal1 frequency on pin xtal1 [2] [3] -48 - 80mhz t (reset) reset pulse width [4] 200 - 200 - ns t su1 address setup time 10 - 10 - ns t su2 data setup time 16 - 16 - ns t w1 cs strobe width 77 - 30 - ns 1 t wclk () -------------- -
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 36 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 11.1 timing diagrams fig 14. general read timing 002aab08 7 t su1 a0 to a3 cs r/w d0 to d7 t w1 t h4 t d2 t d4 t d1 t d3 valid data valid data valid address valid address fig 15. general write timing 002aab08 8 a0 to a3 d0 to d7 cs r/w t d1 t su2 t h3 t h2 t d6 t h4 t w1 t su1 valid data valid data valid address valid address
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 37 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos (1) cs timing during a write cycle. see figure 15 . (2) cs timing during a read cycle. see figure 14 . fig 16. modem input/output timing t d7 change of state t d8 t d8 t d9 002aab08 9 t d8 change of state change of state change of state active active active active active active active change of state rtsa, rtsb dtra, dtrb cs (write) (1) cda, cdb ctsa, ctsb dsra, dsrb irq cs (read) (2) ria, rib fig 17. external clock timing external clock 002aac35 7 t w(clk) t wl t wh f xtal1 1 t wclk () -------------- - =
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 38 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos fig 18. receive timing d0 d1 d2 d3 d4 d5 d6 d7 active active 16 baud rate clock 002aab09 0 t d11 next data start bit stop bit parity bit start bit t d10 rxa, rxb irq cs (read) data bits (0 to 7) 5 data bits 6 data bits 7 data bits fig 19. receive ready timing in non-fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aab091 next data start bit stop bit parity bit t d15 rxa, rxb rxrdya, rxrdyb cs (read) active data ready start bit data bits (0 to 7) active t d16
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 39 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos fig 20. receive ready timing in fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aab092 first byte that reaches the trigger level stop bit parity bit t d15 rxa, rxb rxrdya, rxrdyb cs (read) active data ready start bit data bits (0 to 7) active t d16 fig 21. transmit timing d0 d1 d2 d3 d4 d5 d6 d7 active transmitter ready active 16 baud rate clock 002aab093 t d14 start bit t d12 txa, txb irq cs (write) data bits (0 to 7) active t d13 5 data bits 6 data bits 7 data bits parity bit stop bit next data start bit
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 40 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos fig 22. transmit ready timing in non-fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aab09 4 start bit t d17 txa, txb txrdya, txrdyb cs (write) data bits (0 to 7) active d0 to d7 byte #1 t d18 transmitter not ready active transmitter ready parity bit stop bit next data start bit fig 23. transmit ready timing in fifo mode d0 d1 d2 d3 d4 d5 d6 d7 002aab37 7 stop bit parity bit t d17 txa, txb cs (write) d0 to d7 start bit data bits (0 to 7) byte #64 txrdya, txrdyb t d18 trigger lead active 5 data bits 6 data bits 7 data bits
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 41 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 12. package outline fig 24. package outline sot313-2 (lqfp48) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index l qfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313 -2
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 42 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos fig 25. package outline sot617-1 (hvqfn32) 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 5.1 4.9 d h 3.25 2.95 y 1 5.1 4.9 3.25 2.95 e 1 3.5 e 2 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot617-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot617 -1 h vqfn32: plastic thermal enhanced very thin quad flat package; no leads; 3 2 terminals; body 5 x 5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 916 32 25 24 17 8 1 x d e c b a e 2 terminal 1 index area terminal 1 index area 01-08-08 02-10-18 1/2 e 1/2 e a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 43 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 13. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 44 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 13.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 26 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 2 8 and 29 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 26 . table 28. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 29. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 45 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 14. abbreviations msl: moisture sensitivity level fig 26. temperature profiles for large and small components 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 30. abbreviations acronym description cpu central processing unit dma direct memory access fifo first in/first out lsb least significant bit msb most significant bit pcb printed-circuit board ttl transistor-transistor logic uart universal asynchronous receiver and transmitter
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 46 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 15. revision history table 31. revision history document id release date data sheet status change notice supersedes sc68c752b_4 20100120 product data sheet - sc68c752b_3 modifications: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? descriptive title of data sheet modified: changed from ?motorola? to ?68 mode? ? section 2 ? features ? : ? 1 st bullet item changed from ?motorola p interface? to ?68 mode (motorola) p interface? ? 10 th bullet item changed from ?5 v tolerant inputs? to ?5 v tolerant on input only pins? ? 10 th bullet item added footnote 1 ? table 2 ? pin description ? : added table note [1] and its reference at hvqfn32 pin 13. ? section 7.11 ? divisor latches (dll, dlm) ? : changed from ?dlh? to ?dlm? (and throughout data sheet) ? table 25 ? limiting values ? : ? removed specification for v i ? added specification for v n ? removed table note [1] and its reference (statement is now covered in section 16.3 ) ? table 26 ? static characteristics ? : parameter for i cc(sleep) changed from ?sleep current? to ?sleep mode supply current? ? table 27 ? dynamic characteristics ? : ? added table note [4] and its reference at t (reset) ? split symbol/parameter ?t w1 , t w2 , clock cycle period? to two symbol/parameters, ?t wh , pulse width high? and ?t wl , pulse width low? ? denominator in equation in table note [3] changed from ?t w3 ? to ?t w(clk) ? ? figure 17 ? external clock timing ? : ? changed symbol from ?t w1 ? to ?t wh ? ? changed symbol from ?t w2 ? to ?t wl ? ? changed symbol from ?t w3 ? to ?t w(clk) ? (in both drawing and equation denominator) sc68c752b_3 20051129 product data sheet - sc68c752b_2 sc68c752b_2 (9397 750 14963) 20050428 product data sheet - sc68c752b_1 sc68c752b_1 (9397 750 13857) 20050329 product data sheet - -
sc68c752b_4 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 20 january 2010 47 of 48 nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 16.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 disclaimers general ? information in this document is believed to be accurate and reliable. however, nxp semiconductors d oes not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale ? nxp semiconductors products are sold subject to the general terms and condit ions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writ ing by nxp semiconductors. in case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 16.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
nxp semiconductors sc68c752b 5 v, 3.3 v and 2.5 v dual uart, 5 mbit/s (max.), with 64-byte fifos ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 20 january 2010 document identifier: sc68c752b_4 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 functional description . . . . . . . . . . . . . . . . . . . 7 6.1 trigger levels . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 hardware flow control . . . . . . . . . . . . . . . . . . . . 7 6.2.1 auto-rts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2.2 auto-cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.3 software flow control . . . . . . . . . . . . . . . . . . . . 9 6.3.1 receive flow control . . . . . . . . . . . . . . . . . . . . 10 6.3.2 transmit flow control. . . . . . . . . . . . . . . . . . . . 10 6.3.3 software flow control example . . . . . . . . . . . . 11 6.3.3.1 assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.5.1 interrupt mode operation . . . . . . . . . . . . . . . . 14 6.5.2 polled mode operation . . . . . . . . . . . . . . . . . . 14 6.6 dma operation . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6.1 single dma transfers (dma mode 0/fifo disable). . . . . . . . . . . . . . 15 6.6.1.1 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6.1.2 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6.2 block dma transfers (dma mode 1). . . . . . . . 16 6.6.2.1 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.6.2.2 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.7 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.8 break and time-out conditions . . . . . . . . . . . . 17 6.9 programmable baud rate generator . . . . . . . . 17 7 register descriptions . . . . . . . . . . . . . . . . . . . 19 7.1 receiver holding register (rhr). . . . . . . . . . 21 7.2 transmit holding register (thr) . . . . . . . . . . 21 7.3 fifo control register (fcr) . . . . . . . . . . . . . 22 7.4 line control register (lcr) . . . . . . . . . . . . . . 23 7.5 line status register (lsr) . . . . . . . . . . . . . . . 24 7.6 modem control register (mcr) . . . . . . . . . . . 25 7.7 modem status register (msr) . . . . . . . . . . . . 26 7.8 interrupt enable register (ier) . . . . . . . . . . . 27 7.9 interrupt identific ation register (iir). . . . . . . . 28 7.10 enhanced feature register (efr) . . . . . . . . . 29 7.11 divisor latches (dll, dlm). . . . . . . . . . . . . . . 29 7.12 transmission control register (tcr). . . . . . . 29 7.13 trigger level register (tlr) . . . . . . . . . . . . . 30 7.14 fifo ready register . . . . . . . . . . . . . . . . . . . . 30 8 programmer?s guide . . . . . . . . . . . . . . . . . . . . 31 9 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 33 10 static characteristics . . . . . . . . . . . . . . . . . . . 34 11 dynamic characteristics. . . . . . . . . . . . . . . . . 35 11.1 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 36 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 41 13 soldering of smd packages . . . . . . . . . . . . . . 43 13.1 introduction to soldering. . . . . . . . . . . . . . . . . 43 13.2 wave and reflow soldering. . . . . . . . . . . . . . . 43 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 43 13.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 44 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 45 15 revision history . . . . . . . . . . . . . . . . . . . . . . . 46 16 legal information . . . . . . . . . . . . . . . . . . . . . . 47 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 47 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 47 16.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 47 17 contact information . . . . . . . . . . . . . . . . . . . . 47 18 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

▲Up To Search▲

Price & Availability of SC68C752BIB48

	To Download SC68C752BIB48 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .